1. Field of the Invention
The present invention generally relates to a stacked semiconductor device, and especially relates to a stacked semiconductor device having a three-dimensional structure wherein two or more semiconductor device units and semiconductor devices are stacked.
With advancement of electronic apparatuses in recent years, semiconductor devices used therein are increasingly required to be small in size, thin, capable of providing multiple functions and advanced features, and highly condensed. In order to meet such requirements, the packaging structure of semiconductor devices is shifting to a three-dimensional structure wherein two or more semiconductor device units or two or more semiconductor devices are stacked.
2. Description of the Related Art
Conventionally, semiconductor devices with three-dimensional structures containing two or more semiconductor device units have been disclosed as JPL, 06-252334 (pp. 3 through 7, FIG. 1) (patent reference 1) and JPL, 2002-158312 (pp. 3 through 7, FIG. 1) (patent reference 2) indicate. Here, a semiconductor device unit means a semiconductor device as it is, and a structure containing a semiconductor device in a package. The patent reference 1 discloses a QFP (quad flat package) that employs a leadframe as an external terminal. A QFP type semiconductor device provides a terminal on the upper part of the package by forming a convex section by deforming an inner lead section of the leadframe, on which package a stacking wiring substrate having terminals on both upper and bottom surfaces of the package is connected by a solder bump.
In the case of the patent reference 2, a semiconductor device is disclosed wherein a plurality of molding-sealed semiconductor units are stacked. Here, penetration wiring is provided on the semiconductor device at the molding-seal section of the semiconductor device units such that a terminal is provided at the upper part of the package, at which upper part of the package a re-wiring substrate having a terminal on both upper and bottom surfaces is connected by a solder ball.
Nevertheless, according to the semiconductor device disclosed by the patent reference 1, problems are that no more than one semiconductor device unit can be stacked beneath (i.e., two in total), and that a terminal has to be prepared at the upper part of the package by deforming a leadframe, requiring considerable manufacturing processes, with manufacturing cost becoming high.
According to the semiconductor device disclosed by the patent reference 2, problems are that the stacked end product becomes thick since each semiconductor device unit is molded, and considerable manufacturing processes are required in order to form the penetration wiring, raising manufacturing cost.
Further, in the semiconductor devices as disclosed by the patent references 1 and 2 wherein two or more semiconductor device units are stacked into a three-dimensional structure, it is necessary to set up so as to arrange external connection terminals of each semiconductor device unit such that stacking is possible. This may not pose a problem if the semiconductor device units are newly designed, manufactured, tested, and then stacked. However, there are cases where employing general-purpose semiconductor device units is desired from the economical point of view, given that the general-purpose semiconductor device units have passed tests and are guaranteed for proper operation. In this case, a problem is in that the external connection terminals of each semiconductor device unit are not necessarily set up such that stacking can be carried out.